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Figure 17.9 shows the transmission of a control channel block. This could be either an SDCCH or SACCH accompanying SDCCH. Tasks marked TX include waiting for the frequency synthesizer to lock. The tasks involved are: (i) Passing the data block to be transmitted through the channel encoder and interleaver and adding the midambles, stealing ags and tail bits to produce four 148-bit bursts for transmission. This is shown as task CE in the gure. The main layer 1 state machine triggers it when an SDCCH or accompanying SACCH transmission is required Programming the hardware with the frequency to transmit and time at which to start transmission. This is shown as task P and is triggered by the end of the CE task or by an interrupt at the end of the previous transmit burst if there is one Transferring each burst to the transmit data buffer. This is shown as task T on the diagram. Task T is triggered by the end of task P or by the end of a transmit burst Reprogram the hardware after the nal burst transmission so that another transmission does not occur. This is shown as task Q. It is triggered by the end of the nal transmit burst.

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(ii)

You may also notice that when you first load the program, you don t see the output window. Instead, you see a gray line beneath the buttons. As soon as you click the Find Info button, the information appears where the gray line was. A little CSS3 and HTML5 DOM work does the trick. First, in the CSS3, set up the ID:

(iii)

#profile { display:table-cell; background-color: #979C9C; padding: 3px; width:150px; font-family: Trebuchet MS , Arial, Helvetica, sans-serif; font-size:14px; }

(iv)

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The deadline for task CE, P and the rst task T is 500 s before transmission is due to start, so approximately 1 frame period, since transmission starts three timeslots into the next frame. If a previous transmit operation is in progress the deadline for CE is unchanged, but the deadline for P and T is reduced to six timeslots or 3.4 ms. The subsequent task T invocations are triggered by the end of the transmission and must complete before the start of the next transmission. Hence the deadline there is seven timeslots (3.9 ms).

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Figure 17.10 shows the simultaneous transmission and reception of a control channel block. This only occurs with an SDCCH in one direction and an SACCH accompanying SDCCH in the other. The tasks involved are: (i) Pass the transmit data block through the channel encoder and interleaver (CE). Add midambles, stealing ags and tail bits to produce bursts for transmission. This task is triggered by the main layer 1 state machine when a simultaneous SDCCH receive and transmit is required Programming the hardware with the frequency to receive/transmit and the time at which to start the receive and transmission. This is shown as task P. It is triggered by the end of the CE task or the end of the previous transmit burst if there is one Reading blocks of 16 sample pairs from HW buffer to main memory buffer. This task is triggered by an interrupt from the receive ADC when 16 sample pairs are available. After 10 blocks have been received, task (ii) is triggered

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(iii)

the information stored in this.profile was sent to the Web page where the following tag was placed:

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Prior to HTML5, dynamically sending data to a Web page without reloading the page was far more complex. However, for certain programs like Adobe Flash CS5, it s quite easy, as the next section explains.

Pass the 160 received sample pairs through the normal burst equalizer (EQ). This calculates the precise timing of the burst and demodulates it. This task is triggered by the receive ISR when 160 sample pairs have been received Pass four demodulated bursts through the de-interleaver and channel decoder (CD). This corrects any errors in the received data. This task is triggered by the end of the last EQ task Transfer each traf c burst to the transmit data buffer. This is shown as task T on the diagram. This task is triggered either by the end of the P task or by the end of the previous transmit burst Reprogram the hardware after the nal burst transmission so that another receive/transmit does not occur. This is shown as the task Q. It is triggered by the end of the nal transmit burst.

(vi)

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